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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___config.html">XCsuDma_Config</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csu_dma___configure.html">XCsuDma_Configure</a></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga4fd22ed9ee5ff0eae03ee717112b7087"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga4fd22ed9ee5ff0eae03ee717112b7087">XCsuDma_Reset</a>()</td></tr>
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<tr class="memitem:ga97adf45a00577175416617745ddae9b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga97adf45a00577175416617745ddae9b8">XCsuDma_WaitForDone</a>(InstancePtr,  Channel)</td></tr>
<tr class="separator:ga97adf45a00577175416617745ddae9b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf6f5fdbd1556eecafa2ecf802b88e73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gadf6f5fdbd1556eecafa2ecf802b88e73">XCsuDma_GetDoneCount</a>(InstancePtr,  Channel)</td></tr>
<tr class="separator:gadf6f5fdbd1556eecafa2ecf802b88e73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga055148e26de969504f6b826af3fe9279"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga055148e26de969504f6b826af3fe9279">XCsuDma_GetFIFOLevel</a>(InstancePtr,  Channel)</td></tr>
<tr class="separator:ga055148e26de969504f6b826af3fe9279"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b3c3d44a05b300dd2b60a1f15bc9a60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga8b3c3d44a05b300dd2b60a1f15bc9a60">XCsuDma_GetWROutstandCount</a>(InstancePtr,  Channel)</td></tr>
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<tr class="memitem:gaf15d6d8d487734165214850984ac00f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaf15d6d8d487734165214850984ac00f2">XCsuDma_IsBusy</a>(InstancePtr,  Channel)</td></tr>
<tr class="separator:gaf15d6d8d487734165214850984ac00f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga356d29aa2d43a1b724700007be7dcd51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__csudma__v1__0.html#gae02862bee946eeb9f0684d24550d1afa">XCsuDma_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
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<tr class="memitem:ga5a2390fe93e02061d01c3b9e057b3b2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__csudma__v1__0.html#gae5b5c8718f050b6b4e25380a92c9aa0d">XCsuDma_Out32</a>((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga64394cb7de1a6bc3e31fca2f4a5e59bb"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga64394cb7de1a6bc3e31fca2f4a5e59bb">XCsuDma_CfgInitialize</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="struct_x_csu_dma___config.html">XCsuDma_Config</a> *CfgPtr, u32 EffectiveAddr)</td></tr>
<tr class="separator:ga64394cb7de1a6bc3e31fca2f4a5e59bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace70d2b6c66ded008944dfd456c1bf5c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, UINTPTR Addr, u32 Size, u8 EnDataLast)</td></tr>
<tr class="separator:gace70d2b6c66ded008944dfd456c1bf5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga25049be545d8ec6eae2426b6248a8e4f"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga25049be545d8ec6eae2426b6248a8e4f">XCsuDma_GetAddr</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel)</td></tr>
<tr class="separator:ga25049be545d8ec6eae2426b6248a8e4f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5fd579fb9c166e59ee1f9d3b39250c7"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gad5fd579fb9c166e59ee1f9d3b39250c7">XCsuDma_GetSize</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel)</td></tr>
<tr class="separator:gad5fd579fb9c166e59ee1f9d3b39250c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00b5080126710866186d0bfafd26e9b6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="group__csudma__v1__0.html#gad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a> Type)</td></tr>
<tr class="separator:ga00b5080126710866186d0bfafd26e9b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa3450f812658f927f289b997b12a4174"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaa3450f812658f927f289b997b12a4174">XCsuDma_IsPaused</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="group__csudma__v1__0.html#gad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a> Type)</td></tr>
<tr class="separator:gaa3450f812658f927f289b997b12a4174"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeee3f2d5bcf265b57c9f214f2bc15a28"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="group__csudma__v1__0.html#gad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a> Type)</td></tr>
<tr class="separator:gaeee3f2d5bcf265b57c9f214f2bc15a28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17f1a7ba935f4bf3626050e0b0e0142b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga17f1a7ba935f4bf3626050e0b0e0142b">XCsuDma_GetCheckSum</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr)</td></tr>
<tr class="separator:ga17f1a7ba935f4bf3626050e0b0e0142b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78bdd79674e2b5c92b9701cacfde1fe1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga78bdd79674e2b5c92b9701cacfde1fe1">XCsuDma_ClearCheckSum</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr)</td></tr>
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<tr class="memitem:gac9b6265e467b03cc903cd66781e95e63"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="struct_x_csu_dma___configure.html">XCsuDma_Configure</a> *ConfigurValues)</td></tr>
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<tr class="memitem:gaab0b66bca3f38d26d38ff47544fa6b11"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="struct_x_csu_dma___configure.html">XCsuDma_Configure</a> *ConfigurValues)</td></tr>
<tr class="separator:gaab0b66bca3f38d26d38ff47544fa6b11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1335313d09e43a42b0c1d7276f3b7f67"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_csu_dma___config.html">XCsuDma_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga1335313d09e43a42b0c1d7276f3b7f67">XCsuDma_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="separator:ga1335313d09e43a42b0c1d7276f3b7f67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6169fa380a4d55e41d7ab96589372e8f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga6169fa380a4d55e41d7ab96589372e8f">XCsuDma_IntrGetStatus</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel)</td></tr>
<tr class="separator:ga6169fa380a4d55e41d7ab96589372e8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1db5eabd96920efb06fb03c919420601"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, u32 Mask)</td></tr>
<tr class="separator:ga1db5eabd96920efb06fb03c919420601"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad892a65e65ac14f48f7d7f53020511cf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, u32 Mask)</td></tr>
<tr class="separator:gad892a65e65ac14f48f7d7f53020511cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf3599e4d07ef05586a217ebbbd02999"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, u32 Mask)</td></tr>
<tr class="separator:gadf3599e4d07ef05586a217ebbbd02999"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ed420e8bfd9ab489a2d2c3e984ca7a2"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga6ed420e8bfd9ab489a2d2c3e984ca7a2">XCsuDma_GetIntrMask</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel)</td></tr>
<tr class="separator:ga6ed420e8bfd9ab489a2d2c3e984ca7a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga774ab551d0ef59fd880ff834f2d83804"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga774ab551d0ef59fd880ff834f2d83804">XCsuDma_SelfTest</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr)</td></tr>
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Interrupt Enable/Disable/Mask/Status registers bit masks</h2></td></tr>
<tr class="memitem:ga441edc2ec9eadb8093ac0ab41e0162d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga441edc2ec9eadb8093ac0ab41e0162d2">XCSUDMA_IXR_SRC_MASK</a>&#160;&#160;&#160;0x0000007FU</td></tr>
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<tr class="memitem:gadfb7ef2922c9ceb4804bc87620c35134"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gadfb7ef2922c9ceb4804bc87620c35134">XCSUDMA_IXR_DST_MASK</a>&#160;&#160;&#160;0x000000FEU</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga9d2d57334cfc09d28c8d3d2db98efa1c"></a>
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          <td class="memname">#define XCSU_BASEADDRESS&#160;&#160;&#160;0xFFCA0000</td>
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<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>CSU Base Address. </p>

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          <td class="memname">#define XCSU_DMA_RESET_OFFSET&#160;&#160;&#160;0x0000000CU</td>
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<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>CSU_DMA Reset offset. </p>

</div>
</div>
<a class="anchor" id="ga167f814ecf53fd2228490b5b6d5431df"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_ADDR_LSB_MASK&#160;&#160;&#160;0x00000003U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Address alignment check mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

</div>
</div>
<a class="anchor" id="ga23841a10691cb51210298b0614e67573"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_ADDR_MASK&#160;&#160;&#160;0xFFFFFFFCU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Address mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

</div>
</div>
<a class="anchor" id="ga4d6c9218a21c89c884ef15a38956469b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_ADDR_MSB_OFFSET&#160;&#160;&#160;0x028</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Address's MSB Register Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga25049be545d8ec6eae2426b6248a8e4f">XCsuDma_GetAddr()</a>, and <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

</div>
</div>
<a class="anchor" id="ga76fcd0f2a0c7ebc2058f231a944c7109"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_ADDR_OFFSET&#160;&#160;&#160;0x000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Address Register Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga25049be545d8ec6eae2426b6248a8e4f">XCsuDma_GetAddr()</a>, and <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

</div>
</div>
<a class="anchor" id="ga742012672c371578fc7fce4908f173f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CRC_OFFSET&#160;&#160;&#160;0x010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>CheckSum Register Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga78bdd79674e2b5c92b9701cacfde1fe1">XCsuDma_ClearCheckSum()</a>, and <a class="el" href="group__csudma__v1__0.html#ga17f1a7ba935f4bf3626050e0b0e0142b">XCsuDma_GetCheckSum()</a>.</p>

</div>
</div>
<a class="anchor" id="ga94f131f080543e47020a2fd4d5d4cf7f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CRC_RESET_MASK&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Mask to reset value of check sum. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga78bdd79674e2b5c92b9701cacfde1fe1">XCsuDma_ClearCheckSum()</a>.</p>

</div>
</div>
<a class="anchor" id="ga668128c78f38748fb04d519246453033"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_ACACHE_MASK&#160;&#160;&#160;0X07000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>AXI CACHE mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gab682491284b66d39496860a8333951c7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_ACACHE_SHIFT&#160;&#160;&#160;24U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Shift for AXI R/W CACHE. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="ga56c33f23233637055b848282bbb29cb6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_MAXCMDS_MASK&#160;&#160;&#160;0x0000000FU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Maximum commands mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gabba0bc92253474154042e7eec30f531a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_OFFSET&#160;&#160;&#160;0x024</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Interrupt Control Register 2 Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="ga2994ec3a4ddd8feadffbdeafa27fdd8a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_RESERVED_MASK&#160;&#160;&#160;0x083F0000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Reserved bits mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gadfeec3d6cc61726efa5b38c5465bfe22"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_RESET_MASK&#160;&#160;&#160;0x0000FFF8U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Reset mask. </p>

</div>
</div>
<a class="anchor" id="gac388240ecd8b78fe7a9051eb065e1d00"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_ROUTE_MASK&#160;&#160;&#160;0x00800000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Route mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gaba47338630b6e8aaa756aa442e886bc0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_ROUTE_SHIFT&#160;&#160;&#160;23U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Shift for route. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gad9d80f9c720cd3539b8086c467038432"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK&#160;&#160;&#160;0x00400000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Time out counters enable mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gad4d0b2a2d8b593ac49f879567fd2f076"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT&#160;&#160;&#160;22U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Shift for Timeout enable feild. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="ga9bc4b8e583b6c947023490e817352340"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK&#160;&#160;&#160;0x0000FFF0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Time out pre mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gad1b3913111c69b6bd2be606dbe341ab4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT&#160;&#160;&#160;4U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Shift for Timeout pre feild. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="ga0e6766f31a6332796f3b8ff912c786e5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL_APB_ERR_MASK&#160;&#160;&#160;0x01000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>APB register access error mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gae7479f63823b9eb5f36139fd7414e56a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL_APB_ERR_SHIFT&#160;&#160;&#160;24U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>APB error shift. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gae3c25e9c83a1e84d061746fa01142305"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL_BURST_MASK&#160;&#160;&#160;0x00400000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>AXI burst type mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gaf44a7c00dd4ffbd3405b66a8fac60860"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL_BURST_SHIFT&#160;&#160;&#160;22U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>AXI burst type shift. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="gad5e388818030cd2ca04d9dc867440329"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL_ENDIAN_MASK&#160;&#160;&#160;0x00800000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Endianess mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, <a class="el" href="group__csudma__v1__0.html#ga774ab551d0ef59fd880ff834f2d83804">XCsuDma_SelfTest()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="ga19e7f9c690bdf3c1633ea60845ca1285"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL_ENDIAN_SHIFT&#160;&#160;&#160;23U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Endianess shift. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="ga083616ad7e4d22a9abfd3ab959c1eae4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL_FIFO_THRESH_MASK&#160;&#160;&#160;0x000003FCU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>FIFO threshold mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="ga0ebe79007915c3f88a41b75168fbe8ff"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT&#160;&#160;&#160;2U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>FIFO thresh shift. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="ga60d1ed5209af6a5d9e9c55b6b95052de"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCSUDMA_CTRL_OFFSET&#160;&#160;&#160;0x00C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Control Register Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, <a class="el" href="group__csudma__v1__0.html#gaa3450f812658f927f289b997b12a4174">XCsuDma_IsPaused()</a>, <a class="el" href="group__csudma__v1__0.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause()</a>, <a class="el" href="group__csudma__v1__0.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume()</a>, <a class="el" href="group__csudma__v1__0.html#ga774ab551d0ef59fd880ff834f2d83804">XCsuDma_SelfTest()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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</div>
<a class="anchor" id="ga8bbf92fafd6d0808e8db4a6b772e5b6f"></a>
<div class="memitem">
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          <td class="memname">#define XCSUDMA_CTRL_PAUSE_MEM_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Memory pause mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaa3450f812658f927f289b997b12a4174">XCsuDma_IsPaused()</a>, <a class="el" href="group__csudma__v1__0.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause()</a>, and <a class="el" href="group__csudma__v1__0.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume()</a>.</p>

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<a class="anchor" id="gacdb2f8a8d2b8f782ffec216f6870c0a8"></a>
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          <td class="memname">#define XCSUDMA_CTRL_PAUSE_STRM_MASK&#160;&#160;&#160;0x00000002U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Stream pause mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaa3450f812658f927f289b997b12a4174">XCsuDma_IsPaused()</a>, <a class="el" href="group__csudma__v1__0.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause()</a>, and <a class="el" href="group__csudma__v1__0.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume()</a>.</p>

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<a class="anchor" id="ga1d0f942367f084568b2adfb2b074443a"></a>
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          <td class="memname">#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK&#160;&#160;&#160;0xFE000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>SSS FIFO threshold value mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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<a class="anchor" id="gaba325b1173d26c916097badcff6ab3d5"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT&#160;&#160;&#160;25U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>SSS FIFO threshold shift. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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<a class="anchor" id="ga8f46672097f2d6533df165bbc7bdf0e6"></a>
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        <tr>
          <td class="memname">#define XCSUDMA_CTRL_TIMEOUT_MASK&#160;&#160;&#160;0x003FFC00U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Time out value mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

</div>
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<a class="anchor" id="ga0084f3cdeacc4098f70521b50006025d"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XCSUDMA_CTRL_TIMEOUT_SHIFT&#160;&#160;&#160;10U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Time out value shift. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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<a class="anchor" id="ga37042539804e77b257be674adb88efa4"></a>
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          <td class="memname">#define XCSUDMA_FUTURE_ECO_OFFSET&#160;&#160;&#160;0xFFC</td>
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      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Future potential ECO Offset. </p>

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          <td class="memname">#define XCsuDma_GetDoneCount</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Channel&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>(((InstancePtr)-&gt;Config.BaseAddress), \</div>
<div class="line">                        ((u32)(<a class="code" href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a>) + \</div>
<div class="line">                        ((u32)(Channel) * (u32)(<a class="code" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>)))) &amp; \</div>
<div class="line">                        (u32)(<a class="code" href="group__csudma__v1__0.html#gaf3e6ebc15a10616414fe7f5f089f6086">XCSUDMA_STS_DONE_CNT_MASK</a>)) &gt;&gt; \</div>
<div class="line">                                (u32)(<a class="code" href="group__csudma__v1__0.html#gabe346c87e4cb91d915c4fe93780fe292">XCSUDMA_STS_DONE_CNT_SHIFT</a>))</div>
<div class="ttc" id="group__csudma__v1__0_html_gabe346c87e4cb91d915c4fe93780fe292"><div class="ttname"><a href="group__csudma__v1__0.html#gabe346c87e4cb91d915c4fe93780fe292">XCSUDMA_STS_DONE_CNT_SHIFT</a></div><div class="ttdeci">#define XCSUDMA_STS_DONE_CNT_SHIFT</div><div class="ttdoc">Shift for Count done. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:146</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga8605c51a50a0667f6aff787f25aa55ba"><div class="ttname"><a href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a></div><div class="ttdeci">#define XCSUDMA_OFFSET_DIFF</div><div class="ttdoc">Offset difference for source and destination channels. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:111</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga356d29aa2d43a1b724700007be7dcd51"><div class="ttname"><a href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a></div><div class="ttdeci">#define XCsuDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads the given register. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:333</div></div>
<div class="ttc" id="group__csudma__v1__0_html_gaf3e6ebc15a10616414fe7f5f089f6086"><div class="ttname"><a href="group__csudma__v1__0.html#gaf3e6ebc15a10616414fe7f5f089f6086">XCSUDMA_STS_DONE_CNT_MASK</a></div><div class="ttdeci">#define XCSUDMA_STS_DONE_CNT_MASK</div><div class="ttdoc">Count done mask. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:138</div></div>
<div class="ttc" id="group__csudma__v1__0_html_gaa69407558163d5fc58ac9621b3e313a3"><div class="ttname"><a href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a></div><div class="ttdeci">#define XCSUDMA_STS_OFFSET</div><div class="ttdoc">Status Register Offset. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:72</div></div>
</div><!-- fragment -->
<p>This function returns the number of completed SRC/DST DMA transfers that have not been acknowledged by software based on the channel selection. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Count is number of completed DMA transfers but not acknowledged (Range is 0 to 7).<ul>
<li>000 - All finished transfers have been acknowledged.</li>
<li>Count - Count number of finished transfers are still outstanding.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. C-style signature: u8 XCsuDma_GetDoneCount(<a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> *InstancePtr, XCsuDma_Channel Channel) </dd></dl>

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          <td class="memname">#define XCsuDma_GetFIFOLevel</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Channel&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>(((InstancePtr)-&gt;Config.BaseAddress), \</div>
<div class="line">                        ((u32)(<a class="code" href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a>) + \</div>
<div class="line">                        ((u32)(Channel) * (u32)(<a class="code" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>)))) &amp; \</div>
<div class="line">                        (u32)(<a class="code" href="group__csudma__v1__0.html#gad60406d26eb204edbea24190a400a1f5">XCSUDMA_STS_FIFO_LEVEL_MASK</a>)) &gt;&gt; \</div>
<div class="line">                                        (u32)(<a class="code" href="group__csudma__v1__0.html#ga15463a130472a0432626f963bc2ce7d3">XCSUDMA_STS_FIFO_LEVEL_SHIFT</a>))</div>
<div class="ttc" id="group__csudma__v1__0_html_ga8605c51a50a0667f6aff787f25aa55ba"><div class="ttname"><a href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a></div><div class="ttdeci">#define XCSUDMA_OFFSET_DIFF</div><div class="ttdoc">Offset difference for source and destination channels. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:111</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga356d29aa2d43a1b724700007be7dcd51"><div class="ttname"><a href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a></div><div class="ttdeci">#define XCsuDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads the given register. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:333</div></div>
<div class="ttc" id="group__csudma__v1__0_html_gad60406d26eb204edbea24190a400a1f5"><div class="ttname"><a href="group__csudma__v1__0.html#gad60406d26eb204edbea24190a400a1f5">XCSUDMA_STS_FIFO_LEVEL_MASK</a></div><div class="ttdeci">#define XCSUDMA_STS_FIFO_LEVEL_MASK</div><div class="ttdoc">FIFO level mask. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:139</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga15463a130472a0432626f963bc2ce7d3"><div class="ttname"><a href="group__csudma__v1__0.html#ga15463a130472a0432626f963bc2ce7d3">XCSUDMA_STS_FIFO_LEVEL_SHIFT</a></div><div class="ttdeci">#define XCSUDMA_STS_FIFO_LEVEL_SHIFT</div><div class="ttdoc">Shift for FIFO level. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:149</div></div>
<div class="ttc" id="group__csudma__v1__0_html_gaa69407558163d5fc58ac9621b3e313a3"><div class="ttname"><a href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a></div><div class="ttdeci">#define XCSUDMA_STS_OFFSET</div><div class="ttdoc">Status Register Offset. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:72</div></div>
</div><!-- fragment -->
<p>This function returns the current SRC/DST FIFO level in 32 bit words of the selected channel. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>FIFO level. (Range is 0 to 128)<ul>
<li>0 Indicates empty</li>
<li>Any number 1 to 128 indicates the number of entries in FIFO.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. C-style signature: u8 XCsuDma_GetFIFOLevel(<a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> *InstancePtr, XCsuDma_Channel Channel) </dd></dl>

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<a class="anchor" id="ga8b3c3d44a05b300dd2b60a1f15bc9a60"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XCsuDma_GetWROutstandCount</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Channel&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>(((InstancePtr)-&gt;Config.BaseAddress), \</div>
<div class="line">                                ((u32)(<a class="code" href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a>) + \</div>
<div class="line">                        ((u32)(Channel) * (u32)(<a class="code" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>)))) &amp; \</div>
<div class="line">                        (u32)(<a class="code" href="group__csudma__v1__0.html#ga56a8b1f3c33817adbe8a131a227a4564">XCUSDMA_STS_OUTSTDG_MASK</a>)) &gt;&gt; \</div>
<div class="line">                                (u32)(<a class="code" href="group__csudma__v1__0.html#gad6719cf8d08f8710300ce922f6e52e40">XCUSDMA_STS_OUTSTDG_SHIFT</a>))</div>
<div class="ttc" id="group__csudma__v1__0_html_gad6719cf8d08f8710300ce922f6e52e40"><div class="ttname"><a href="group__csudma__v1__0.html#gad6719cf8d08f8710300ce922f6e52e40">XCUSDMA_STS_OUTSTDG_SHIFT</a></div><div class="ttdeci">#define XCUSDMA_STS_OUTSTDG_SHIFT</div><div class="ttdoc">Shift for No.of outstanding read/write commands. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:152</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga56a8b1f3c33817adbe8a131a227a4564"><div class="ttname"><a href="group__csudma__v1__0.html#ga56a8b1f3c33817adbe8a131a227a4564">XCUSDMA_STS_OUTSTDG_MASK</a></div><div class="ttdeci">#define XCUSDMA_STS_OUTSTDG_MASK</div><div class="ttdoc">No.of outstanding read/write commands mask. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:140</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga8605c51a50a0667f6aff787f25aa55ba"><div class="ttname"><a href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a></div><div class="ttdeci">#define XCSUDMA_OFFSET_DIFF</div><div class="ttdoc">Offset difference for source and destination channels. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:111</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga356d29aa2d43a1b724700007be7dcd51"><div class="ttname"><a href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a></div><div class="ttdeci">#define XCsuDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads the given register. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:333</div></div>
<div class="ttc" id="group__csudma__v1__0_html_gaa69407558163d5fc58ac9621b3e313a3"><div class="ttname"><a href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a></div><div class="ttdeci">#define XCSUDMA_STS_OFFSET</div><div class="ttdoc">Status Register Offset. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:72</div></div>
</div><!-- fragment -->
<p>This function returns the current number of read(src)/write(dst) outstanding commands based on the type of channel selected. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Count of outstanding commands. (Range is 0 to 9).</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. C-style signature: u8 XCsuDma_GetWROutstandCount(<a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> *InstancePtr, XCsuDma_Channel Channel) </dd></dl>

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<a class="anchor" id="ga8ee71e015a72b9441ead3a0f5541777c"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XCSUDMA_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>

<p>Prevent circular inclusions by using protection macros. </p>

</div>
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<a class="anchor" id="gaf7ae40275005f5b2c827da41a0e3cc23"></a>
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<div class="memproto">
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          <td class="memname">#define XCSUDMA_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Prevent circular inclusions by using protection macros. </p>

</div>
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          <td class="memname">#define XCSUDMA_I_DIS_OFFSET&#160;&#160;&#160;0x01C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Interrupt Disable Register Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr()</a>.</p>

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<a class="anchor" id="ga0f05af1a6ce895ebbd4bdb099ead152c"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XCSUDMA_I_EN_OFFSET&#160;&#160;&#160;0x018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Interrupt Enable Register Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr()</a>.</p>

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<a class="anchor" id="ga6072e9b915ebf29b27cddaa7478aade0"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XCSUDMA_I_MASK_OFFSET&#160;&#160;&#160;0x020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Interrupt Mask Register Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga6ed420e8bfd9ab489a2d2c3e984ca7a2">XCsuDma_GetIntrMask()</a>.</p>

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<a class="anchor" id="gab56adb100901bb2b042a842619064ce5"></a>
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        <tr>
          <td class="memname">#define XCSUDMA_I_STS_OFFSET&#160;&#160;&#160;0x014</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Interrupt Status Register Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear()</a>, and <a class="el" href="group__csudma__v1__0.html#ga6169fa380a4d55e41d7ab96589372e8f">XCsuDma_IntrGetStatus()</a>.</p>

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<a class="anchor" id="gae02862bee946eeb9f0684d24550d1afa"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XCsuDma_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Input operation. </p>

</div>
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          <td class="memname">#define XCsuDma_IsBusy</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Channel&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>(((InstancePtr)-&gt;Config.BaseAddress), \</div>
<div class="line">                                        ((u32)(<a class="code" href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a>) + \</div>
<div class="line">                        ((u32)(Channel) * (u32)(<a class="code" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>)))) &amp; \</div>
<div class="line">                (u32)(<a class="code" href="group__csudma__v1__0.html#ga446c26de02f645feea8f4d38a432ef67">XCSUDMA_STS_BUSY_MASK</a>)) == (<a class="code" href="group__csudma__v1__0.html#ga446c26de02f645feea8f4d38a432ef67">XCSUDMA_STS_BUSY_MASK</a>)) ? \</div>
<div class="line">                                (TRUE) : (FALSE)</div>
<div class="ttc" id="group__csudma__v1__0_html_ga8605c51a50a0667f6aff787f25aa55ba"><div class="ttname"><a href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a></div><div class="ttdeci">#define XCSUDMA_OFFSET_DIFF</div><div class="ttdoc">Offset difference for source and destination channels. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:111</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga356d29aa2d43a1b724700007be7dcd51"><div class="ttname"><a href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a></div><div class="ttdeci">#define XCsuDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads the given register. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:333</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga446c26de02f645feea8f4d38a432ef67"><div class="ttname"><a href="group__csudma__v1__0.html#ga446c26de02f645feea8f4d38a432ef67">XCSUDMA_STS_BUSY_MASK</a></div><div class="ttdeci">#define XCSUDMA_STS_BUSY_MASK</div><div class="ttdoc">Busy mask. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:145</div></div>
<div class="ttc" id="group__csudma__v1__0_html_gaa69407558163d5fc58ac9621b3e313a3"><div class="ttname"><a href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a></div><div class="ttdeci">#define XCSUDMA_STS_OFFSET</div><div class="ttdoc">Status Register Offset. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:72</div></div>
</div><!-- fragment -->
<p>This function returns the status of Channel either it is busy or not. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the current status of the core.<ul>
<li>TRUE represents core is currently busy.</li>
<li>FALSE represents core is not involved in any transfers.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. C-style signature: s32 <a class="el" href="group__csudma__v1__0.html#gaf15d6d8d487734165214850984ac00f2" title="This function returns the status of Channel either it is busy or not. ">XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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<a class="anchor" id="gac6e2bc9f25b7160249710c395a74d933"></a>
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<div class="memproto">
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          <td class="memname">#define XCSUDMA_IXR_AXI_WRERR_MASK&#160;&#160;&#160;0x00000004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>AXI Read/Write error mask. </p>

</div>
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<a class="anchor" id="ga0dbd333c70de601e769b8542552eb7e4"></a>
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          <td class="memname">#define XCSUDMA_IXR_DONE_MASK&#160;&#160;&#160;0x00000002U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Done mask. </p>

</div>
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<a class="anchor" id="gadfb7ef2922c9ceb4804bc87620c35134"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XCSUDMA_IXR_DST_MASK&#160;&#160;&#160;0x000000FEU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) | (XCSUDMA_IXR_INVALID_APB_MASK) | (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK)) </p>
<p>All interrupt mask for destination </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr()</a>, <a class="el" href="group__csudma__v1__0.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr()</a>, and <a class="el" href="group__csudma__v1__0.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear()</a>.</p>

</div>
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<a class="anchor" id="ga33dc1a1076170c9ca47df1c3451bdfe5"></a>
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          <td class="memname">#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>FIFO overflow mask, it is valid only to Destination Channel. </p>

</div>
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<a class="anchor" id="gaf727ccf4d9bbbce46d61f67be041b40c"></a>
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          <td class="memname">#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK&#160;&#160;&#160;0x00000020U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>FIFO threshold hit indicator mask. </p>

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<a class="anchor" id="ga6e7d15f2dfaa7afef685f382db12c62e"></a>
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          <td class="memname">#define XCSUDMA_IXR_INVALID_APB_MASK&#160;&#160;&#160;0x00000040U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Invalid APB access mask. </p>

</div>
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<a class="anchor" id="ga670d9fac28bd9de6b6f6abcb5fda64cc"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XCSUDMA_IXR_MEM_DONE_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Memory done mask, it is valid only for source channel. </p>

</div>
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<a class="anchor" id="ga441edc2ec9eadb8093ac0ab41e0162d2"></a>
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<div class="memproto">
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          <td class="memname">#define XCSUDMA_IXR_SRC_MASK&#160;&#160;&#160;0x0000007FU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>((XCSUDMA_IXR_INVALID_APB_MASK)| (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK) | (XCSUDMA_IXR_MEM_DONE_MASK)) </p>
<p>All interrupt mask for source </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr()</a>, <a class="el" href="group__csudma__v1__0.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr()</a>, and <a class="el" href="group__csudma__v1__0.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear()</a>.</p>

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<a class="anchor" id="gadb917cad64699bd0fc6e21c1fec74068"></a>
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          <td class="memname">#define XCSUDMA_IXR_TIMEOUT_MEM_MASK&#160;&#160;&#160;0x00000010U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Time out counter expired to access memory mask. </p>

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<a class="anchor" id="ga7fc13f5152cf0098d76d4b78b08702e8"></a>
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          <td class="memname">#define XCSUDMA_IXR_TIMEOUT_STRM_MASK&#160;&#160;&#160;0x00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Time out counter expired to access stream mask. </p>

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<a class="anchor" id="gaf0a5114bb4e675c0e9d933a2d235ac6f"></a>
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          <td class="memname">#define XCSUDMA_LAST_WORD_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Last word check bit mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

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<a class="anchor" id="ga29841329ffd65ef1b49870b89171188d"></a>
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<div class="memproto">
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          <td class="memname">#define XCSUDMA_MSB_ADDR_MASK&#160;&#160;&#160;0x0001FFFFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>MSB bits of address mask. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

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</div>
<a class="anchor" id="ga8cb51c5b9c07f84acf19defd57ae764b"></a>
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          <td class="memname">#define XCSUDMA_MSB_ADDR_SHIFT&#160;&#160;&#160;32U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Shift for MSB bits of address. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga25049be545d8ec6eae2426b6248a8e4f">XCsuDma_GetAddr()</a>, and <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

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<a class="anchor" id="ga8605c51a50a0667f6aff787f25aa55ba"></a>
<div class="memitem">
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          <td class="memname">#define XCSUDMA_OFFSET_DIFF&#160;&#160;&#160;0x00000800U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Offset difference for source and destination channels. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr()</a>, <a class="el" href="group__csudma__v1__0.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr()</a>, <a class="el" href="group__csudma__v1__0.html#ga25049be545d8ec6eae2426b6248a8e4f">XCsuDma_GetAddr()</a>, <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, <a class="el" href="group__csudma__v1__0.html#ga6ed420e8bfd9ab489a2d2c3e984ca7a2">XCsuDma_GetIntrMask()</a>, <a class="el" href="group__csudma__v1__0.html#gad5fd579fb9c166e59ee1f9d3b39250c7">XCsuDma_GetSize()</a>, <a class="el" href="group__csudma__v1__0.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear()</a>, <a class="el" href="group__csudma__v1__0.html#ga6169fa380a4d55e41d7ab96589372e8f">XCsuDma_IntrGetStatus()</a>, <a class="el" href="group__csudma__v1__0.html#gaa3450f812658f927f289b997b12a4174">XCsuDma_IsPaused()</a>, <a class="el" href="group__csudma__v1__0.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause()</a>, <a class="el" href="group__csudma__v1__0.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume()</a>, <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

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<a class="anchor" id="gae5b5c8718f050b6b4e25380a92c9aa0d"></a>
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          <td class="memname">#define XCsuDma_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Output operation. </p>

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<a class="anchor" id="ga356d29aa2d43a1b724700007be7dcd51"></a>
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          <td class="memname">#define XCsuDma_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__csudma__v1__0.html#gae02862bee946eeb9f0684d24550d1afa">XCsuDma_In32</a>((BaseAddress) + (u32)(RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>This macro reads the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the Xilinx base address of the CSU_DMA core. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51" title="This macro reads the given register. ">XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga25049be545d8ec6eae2426b6248a8e4f">XCsuDma_GetAddr()</a>, <a class="el" href="group__csudma__v1__0.html#ga17f1a7ba935f4bf3626050e0b0e0142b">XCsuDma_GetCheckSum()</a>, <a class="el" href="group__csudma__v1__0.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, <a class="el" href="group__csudma__v1__0.html#ga6ed420e8bfd9ab489a2d2c3e984ca7a2">XCsuDma_GetIntrMask()</a>, <a class="el" href="group__csudma__v1__0.html#gad5fd579fb9c166e59ee1f9d3b39250c7">XCsuDma_GetSize()</a>, <a class="el" href="group__csudma__v1__0.html#ga6169fa380a4d55e41d7ab96589372e8f">XCsuDma_IntrGetStatus()</a>, <a class="el" href="group__csudma__v1__0.html#gaa3450f812658f927f289b997b12a4174">XCsuDma_IsPaused()</a>, <a class="el" href="group__csudma__v1__0.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause()</a>, <a class="el" href="group__csudma__v1__0.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume()</a>, <a class="el" href="group__csudma__v1__0.html#ga774ab551d0ef59fd880ff834f2d83804">XCsuDma_SelfTest()</a>, and <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">#define XCsuDma_Reset</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">Xil_Out32(((u32)(<a class="code" href="group__csudma__v1__0.html#ga9d2d57334cfc09d28c8d3d2db98efa1c">XCSU_BASEADDRESS</a>) + (u32)(<a class="code" href="group__csudma__v1__0.html#ga70f2106fc1dd240a5ea17386eb46068d">XCSU_DMA_RESET_OFFSET</a>)), \</div>
<div class="line">                                (u32)(<a class="code" href="group__csudma__v1__0.html#ga855c83156a1c7b89b30f1e1dfc23b3fe">XCSUDMA_RESET_SET_MASK</a>)); \</div>
<div class="line">        Xil_Out32(((u32)(<a class="code" href="group__csudma__v1__0.html#ga9d2d57334cfc09d28c8d3d2db98efa1c">XCSU_BASEADDRESS</a>) + (u32)(<a class="code" href="group__csudma__v1__0.html#ga70f2106fc1dd240a5ea17386eb46068d">XCSU_DMA_RESET_OFFSET</a>)), \</div>
<div class="line">                                        (u32)(<a class="code" href="group__csudma__v1__0.html#gace5f08f560599a1164f9a65cfd1cd75f">XCSUDMA_RESET_UNSET_MASK</a>));</div>
<div class="ttc" id="group__csudma__v1__0_html_ga9d2d57334cfc09d28c8d3d2db98efa1c"><div class="ttname"><a href="group__csudma__v1__0.html#ga9d2d57334cfc09d28c8d3d2db98efa1c">XCSU_BASEADDRESS</a></div><div class="ttdeci">#define XCSU_BASEADDRESS</div><div class="ttdoc">CSU Base Address. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:96</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga70f2106fc1dd240a5ea17386eb46068d"><div class="ttname"><a href="group__csudma__v1__0.html#ga70f2106fc1dd240a5ea17386eb46068d">XCSU_DMA_RESET_OFFSET</a></div><div class="ttdeci">#define XCSU_DMA_RESET_OFFSET</div><div class="ttdoc">CSU_DMA Reset offset. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:98</div></div>
<div class="ttc" id="group__csudma__v1__0_html_gace5f08f560599a1164f9a65cfd1cd75f"><div class="ttname"><a href="group__csudma__v1__0.html#gace5f08f560599a1164f9a65cfd1cd75f">XCSUDMA_RESET_UNSET_MASK</a></div><div class="ttdeci">#define XCSUDMA_RESET_UNSET_MASK</div><div class="ttdoc">Reset unset mask. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:105</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga855c83156a1c7b89b30f1e1dfc23b3fe"><div class="ttname"><a href="group__csudma__v1__0.html#ga855c83156a1c7b89b30f1e1dfc23b3fe">XCSUDMA_RESET_SET_MASK</a></div><div class="ttdeci">#define XCSUDMA_RESET_SET_MASK</div><div class="ttdoc">Reset set mask. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:104</div></div>
</div><!-- fragment -->
<p>This function resets the CSU_DMA core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. C-style signature: void <a class="el" href="group__csudma__v1__0.html#ga4fd22ed9ee5ff0eae03ee717112b7087" title="This function resets the CSU_DMA core. ">XCsuDma_Reset()</a> </dd></dl>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga64394cb7de1a6bc3e31fca2f4a5e59bb">XCsuDma_CfgInitialize()</a>.</p>

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<a class="anchor" id="ga855c83156a1c7b89b30f1e1dfc23b3fe"></a>
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          <td class="memname">#define XCSUDMA_RESET_SET_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Reset set mask. </p>

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<a class="anchor" id="gace5f08f560599a1164f9a65cfd1cd75f"></a>
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          <td class="memname">#define XCSUDMA_RESET_UNSET_MASK&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Reset unset mask. </p>

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<a class="anchor" id="ga356c14c3ccd1db0253b2db102be41663"></a>
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          <td class="memname">#define XCSUDMA_SAFETY_CHK_OFFSET&#160;&#160;&#160;0xFF8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Safety Check Field Offset. </p>

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<a class="anchor" id="ga2e9db5623d0c9b85088c528d43c9b411"></a>
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          <td class="memname">#define XCSUDMA_SIZE_MASK&#160;&#160;&#160;0x1FFFFFFCU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Mask for size. </p>

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<a class="anchor" id="gab57550413ed1c53f70a33ad4b90965eb"></a>
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<div class="memproto">
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          <td class="memname">#define XCSUDMA_SIZE_MAX&#160;&#160;&#160;0x07FFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>

<p>Maximum allowed no of words. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

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<a class="anchor" id="gaf5d3e01cba7a5d0029901f690007a9c0"></a>
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          <td class="memname">#define XCSUDMA_SIZE_OFFSET&#160;&#160;&#160;0x004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Size Register Offset. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gad5fd579fb9c166e59ee1f9d3b39250c7">XCsuDma_GetSize()</a>, and <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

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<a class="anchor" id="gae1d5689d4fbd05c2e7f6b2a34bcbfb09"></a>
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          <td class="memname">#define XCSUDMA_SIZE_SHIFT&#160;&#160;&#160;2U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Shift for size. </p>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#gad5fd579fb9c166e59ee1f9d3b39250c7">XCsuDma_GetSize()</a>, and <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

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<a class="anchor" id="ga446c26de02f645feea8f4d38a432ef67"></a>
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          <td class="memname">#define XCSUDMA_STS_BUSY_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Busy mask. </p>

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<a class="anchor" id="gaf3e6ebc15a10616414fe7f5f089f6086"></a>
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          <td class="memname">#define XCSUDMA_STS_DONE_CNT_MASK&#160;&#160;&#160;0x0000E000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Count done mask. </p>

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<a class="anchor" id="gabe346c87e4cb91d915c4fe93780fe292"></a>
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          <td class="memname">#define XCSUDMA_STS_DONE_CNT_SHIFT&#160;&#160;&#160;13U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Shift for Count done. </p>

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<a class="anchor" id="gad60406d26eb204edbea24190a400a1f5"></a>
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          <td class="memname">#define XCSUDMA_STS_FIFO_LEVEL_MASK&#160;&#160;&#160;0x00001FE0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>FIFO level mask. </p>

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<a class="anchor" id="ga15463a130472a0432626f963bc2ce7d3"></a>
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          <td class="memname">#define XCSUDMA_STS_FIFO_LEVEL_SHIFT&#160;&#160;&#160;5U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Shift for FIFO level. </p>

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<a class="anchor" id="gaa69407558163d5fc58ac9621b3e313a3"></a>
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          <td class="memname">#define XCSUDMA_STS_OFFSET&#160;&#160;&#160;0x008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Status Register Offset. </p>

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          <td class="memname">#define XCsuDma_WaitForDone</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Channel&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><span class="keywordflow">while</span>((<a class="code" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>(((InstancePtr)-&gt;Config.BaseAddress), \</div>
<div class="line">                        ((u32)(<a class="code" href="group__csudma__v1__0.html#gab56adb100901bb2b042a842619064ce5">XCSUDMA_I_STS_OFFSET</a>) + \</div>
<div class="line">                        ((u32)(Channel) * (u32)(<a class="code" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>)))) &amp; \</div>
<div class="line">                (u32)(<a class="code" href="group__csudma__v1__0.html#ga0dbd333c70de601e769b8542552eb7e4">XCSUDMA_IXR_DONE_MASK</a>)) != (<a class="code" href="group__csudma__v1__0.html#ga0dbd333c70de601e769b8542552eb7e4">XCSUDMA_IXR_DONE_MASK</a>))</div>
<div class="ttc" id="group__csudma__v1__0_html_ga0dbd333c70de601e769b8542552eb7e4"><div class="ttname"><a href="group__csudma__v1__0.html#ga0dbd333c70de601e769b8542552eb7e4">XCSUDMA_IXR_DONE_MASK</a></div><div class="ttdeci">#define XCSUDMA_IXR_DONE_MASK</div><div class="ttdoc">Done mask. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:243</div></div>
<div class="ttc" id="group__csudma__v1__0_html_gab56adb100901bb2b042a842619064ce5"><div class="ttname"><a href="group__csudma__v1__0.html#gab56adb100901bb2b042a842619064ce5">XCSUDMA_I_STS_OFFSET</a></div><div class="ttdeci">#define XCSUDMA_I_STS_OFFSET</div><div class="ttdoc">Interrupt Status Register Offset. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:75</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga8605c51a50a0667f6aff787f25aa55ba"><div class="ttname"><a href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a></div><div class="ttdeci">#define XCSUDMA_OFFSET_DIFF</div><div class="ttdoc">Offset difference for source and destination channels. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:111</div></div>
<div class="ttc" id="group__csudma__v1__0_html_ga356d29aa2d43a1b724700007be7dcd51"><div class="ttname"><a href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a></div><div class="ttdeci">#define XCsuDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads the given register. </div><div class="ttdef"><b>Definition:</b> xcsudma_hw.h:333</div></div>
</div><!-- fragment -->
<p>This function will be in busy while loop until the data transfer is completed. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function should be called after XCsuDma_Transfer in polled mode to wait until the data gets transfered completely. C-style signature: void XCsuDma_WaitForDone(<a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> *InstancePtr, XCsuDma_Channel Channel) </dd></dl>

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          <td class="memname">#define XCsuDma_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__csudma__v1__0.html#gae5b5c8718f050b6b4e25380a92c9aa0d">XCsuDma_Out32</a>((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>This macro writes the value into the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the Xilinx base address of the CSU_DMA core. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b" title="This macro writes the value into the given register. ">XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__csudma__v1__0.html#ga78bdd79674e2b5c92b9701cacfde1fe1">XCsuDma_ClearCheckSum()</a>, <a class="el" href="group__csudma__v1__0.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr()</a>, <a class="el" href="group__csudma__v1__0.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr()</a>, <a class="el" href="group__csudma__v1__0.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear()</a>, <a class="el" href="group__csudma__v1__0.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause()</a>, <a class="el" href="group__csudma__v1__0.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume()</a>, <a class="el" href="group__csudma__v1__0.html#ga774ab551d0ef59fd880ff834f2d83804">XCsuDma_SelfTest()</a>, <a class="el" href="group__csudma__v1__0.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>, and <a class="el" href="group__csudma__v1__0.html#gace70d2b6c66ded008944dfd456c1bf5c">XCsuDma_Transfer()</a>.</p>

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          <td class="memname">#define XCUSDMA_STS_OUTSTDG_MASK&#160;&#160;&#160;0x0000001EU</td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>No.of outstanding read/write commands mask. </p>

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          <td class="memname">#define XCUSDMA_STS_OUTSTDG_SHIFT&#160;&#160;&#160;1U</td>
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<p><code>#include &lt;<a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>&gt;</code></p>

<p>Shift for No.of outstanding read/write commands. </p>

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<h2 class="groupheader">Enumeration Type Documentation</h2>
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          <td class="memname">enum <a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d"></a>XCSUDMA_SRC_CHANNEL&#160;</td><td class="fielddoc">
<p>Source Channel of CSU_DMA. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4"></a>XCSUDMA_DST_CHANNEL&#160;</td><td class="fielddoc">
<p>Destination Channel of CSU_DMA. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="group__csudma__v1__0.html#gad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="ggad5ce08d197288cbdfb06941f1d46df87a4848b0d503f02b0b03be6cd1a14ef6a8"></a>XCSUDMA_PAUSE_MEMORY&#160;</td><td class="fielddoc">
<p>Pauses memory data transfer to/from CSU_DMA. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="ggad5ce08d197288cbdfb06941f1d46df87a67086fbe749ed37f5928c211ee6aa5b8"></a>XCSUDMA_PAUSE_STREAM&#160;</td><td class="fielddoc">
<p>Pauses stream data transfer to/from CSU_DMA. </p>
</td></tr>
</table>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">s32 XCsuDma_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma___config.html">XCsuDma_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function initializes an CSU_DMA core. </p>
<p>This function must be called prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting up the instance data and ensuring the hardware is in a quiescent state.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>is a reference to a structure containing information about a specific <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, pass in the physical address instead.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if initialization was successful.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, and <a class="el" href="group__csudma__v1__0.html#ga4fd22ed9ee5ff0eae03ee717112b7087">XCsuDma_Reset</a>.</p>

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          <td class="memname">void XCsuDma_ClearCheckSum </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function clears the check sum of the data read from AXI memory. </p>
<p>It is valid only for CSU_DMA source channel.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the sum of all the data read from memory.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Before start of the transfer need to clear this register to get correct sum otherwise it adds to previous value which results to wrong output. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#ga742012672c371578fc7fce4908f173f6">XCSUDMA_CRC_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga94f131f080543e47020a2fd4d5d4cf7f">XCSUDMA_CRC_RESET_MASK</a>, and <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">void XCsuDma_DisableIntr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>

<p>This function disables the interrupt(s). </p>
<p>Use the XCSUDMA_IXR_*_MASK constants defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a> to create the bit-mask to disable interrupts.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Mask</td><td>contains interrupts to be disabled.<ul>
<li>Bit positions of 1 will be disabled. This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#ga302a6020f0d9a857d490320f4a20c873">XCSUDMA_I_DIS_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#gadfb7ef2922c9ceb4804bc87620c35134">XCSUDMA_IXR_DST_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga441edc2ec9eadb8093ac0ab41e0162d2">XCSUDMA_IXR_SRC_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">void XCsuDma_EnableIntr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>

<p>This function enables the interrupt(s). </p>
<p>Use the XCSUDMA_IXR_*_MASK constants defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a> to create the bit-mask to enable interrupts.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Mask</td><td>contains interrupts to be enabled.<ul>
<li>Bit positions of 1 will be enabled. This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#ga0f05af1a6ce895ebbd4bdb099ead152c">XCSUDMA_I_EN_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#gadfb7ef2922c9ceb4804bc87620c35134">XCSUDMA_IXR_DST_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga441edc2ec9eadb8093ac0ab41e0162d2">XCSUDMA_IXR_SRC_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">u64 XCsuDma_GetAddr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function returns the current address location of the memory, from where it has to read the data(SRC) or the location where it has to write the data (DST) based on the channel selection. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Address is a 64 bit variable which holds the current address.<ul>
<li>From this location data has to be read(SRC)</li>
<li>At this location data has to be written(DST)</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#ga4d6c9218a21c89c884ef15a38956469b">XCSUDMA_ADDR_MSB_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga76fcd0f2a0c7ebc2058f231a944c7109">XCSUDMA_ADDR_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#ga8cb51c5b9c07f84acf19defd57ae764b">XCSUDMA_MSB_ADDR_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">u32 XCsuDma_GetCheckSum </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function returns the sum of all the data read from AXI memory. </p>
<p>It is valid only one we use CSU_DMA source channel.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the sum of all the data read from memory.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Before start of the transfer need to clear this register to get correct sum otherwise it adds to previous value which results to wrong output. Valid only for source channel </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="group__csudma__v1__0.html#ga742012672c371578fc7fce4908f173f6">XCSUDMA_CRC_OFFSET</a>, and <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>.</p>

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          <td class="memname">void XCsuDma_GetConfig </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma___configure.html">XCsuDma_Configure</a> *&#160;</td>
          <td class="paramname"><em>ConfigurValues</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function updates <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which needs to be set before the start of the data...">XCsuDma_Configure</a> structure members with the cofigured values of CSU_DMA's Channel. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">ConfigurValues</td><td>is a pointer to the structure <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which needs to be set before the start of the data...">XCsuDma_Configure</a> whose members are updated with configurations of CSU_DMA core.<ul>
<li>SssFifoThesh When the DST FIFO level &gt;= this value, the SSS interface signal, "data_out_fifo_level_hit" will be asserted. This mechanism can be used by the SSS to flow control data that is being looped back from the SRC DMA.<ul>
<li>Range is (0x10 to 0x7A) threshold is 17 to 123 entries.</li>
<li>It is valid only for DST CSU_DMA IP.</li>
</ul>
</li>
<li>ApbErr When accessed to invalid APB the resulting pslerr will be<ul>
<li>0 - 1'b0</li>
<li>1 - 1'b1</li>
</ul>
</li>
<li>EndianType Type of endianness<ul>
<li>0 doesn't change order</li>
<li>1 will flip the order.</li>
</ul>
</li>
<li>AxiBurstType....Type of the burst<ul>
<li>0 will issue INCR type burst</li>
<li>1 will issue FIXED type burst</li>
</ul>
</li>
<li>TimeoutValue Time out value for timers<ul>
<li>0x000 to 0xFFE are valid inputs</li>
<li>0xFFF clears both timers</li>
</ul>
</li>
<li>FifoThresh......Programmed watermark value<ul>
<li>Range is 0x00 to 0x80 (0 to 128 entries).</li>
</ul>
</li>
<li>Acache Sets the AXI CACHE bits on the AXI Write/Read channel.<ul>
<li>Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] for DST channel are always 1, we need to configure remaining 3 signal support (Bufferable, Read allocate and Write allocate). Valid inputs are:</li>
<li>0x000 - Cacheable, but do not allocate</li>
<li>0x001 - Cacheable and bufferable, but do not allocate</li>
<li>0x010 - Cacheable write-through, allocate on reads only</li>
<li>0x011 - Cacheable write-back, allocate on reads only</li>
<li>0x100 - Cacheable write-through, allocate on writes only</li>
<li>0x101 - Cacheable write-back, allocate on writes only</li>
<li>0x110 - Cacheable write-through, allocate on both reads and writes</li>
<li>0x111 - Cacheable write-back, allocate on both reads and writes</li>
</ul>
</li>
<li>RouteBit To select route<ul>
<li>0 : Command will be routed based normally</li>
<li>1 : Command will be routed to APU's cache controller</li>
</ul>
</li>
<li>TimeoutEn To enable or disable time out counters<ul>
<li>0 : The 2 Timeout counters are disabled</li>
<li>1 : The 2 Timeout counters are enabled</li>
</ul>
</li>
<li>TimeoutPre Set the prescaler value for the timeout in clk (~2.5ns) cycles<ul>
<li>Range is 0x000(Prescaler enables timer every cycles) to 0xFFF(Prescaler enables timer every 4096 cycles)</li>
</ul>
</li>
<li>MaxOutCmds Controls the maximumum number of outstanding AXI read commands issued.<ul>
<li>Range is 0x0(Up to 1 Outstanding Read command allowed) to 0x8 (Up to 9 Outstanding Read command allowed)</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___configure.html#a984f69d8fa925618e85800ba8fd2d155">XCsuDma_Configure::Acache</a>, <a class="el" href="struct_x_csu_dma___configure.html#a7ca88dbe204c7b24ce7e529da53e1ae2">XCsuDma_Configure::ApbErr</a>, <a class="el" href="struct_x_csu_dma___configure.html#a1aeadd99f4f96da636b9cb0c2be21c09">XCsuDma_Configure::AxiBurstType</a>, <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma___configure.html#a4d1217d471a558f54534c15213bbb264">XCsuDma_Configure::EndianType</a>, <a class="el" href="struct_x_csu_dma___configure.html#af17af84045f926ff8e386509cc0c9aee">XCsuDma_Configure::FifoThresh</a>, <a class="el" href="struct_x_csu_dma___configure.html#acdf6a30da74f891648e17d1ce9bfadae">XCsuDma_Configure::MaxOutCmds</a>, <a class="el" href="struct_x_csu_dma___configure.html#ac6f8c811d5b1ecf86d37091fc132717e">XCsuDma_Configure::RouteBit</a>, <a class="el" href="struct_x_csu_dma___configure.html#a524260e03c75bc8745da0e4b7dca71ed">XCsuDma_Configure::SssFifoThesh</a>, <a class="el" href="struct_x_csu_dma___configure.html#a2f45ba702e0487ed32152186339d7052">XCsuDma_Configure::TimeoutEn</a>, <a class="el" href="struct_x_csu_dma___configure.html#a00365f4d0973fcb3fd39382312775748">XCsuDma_Configure::TimeoutPre</a>, <a class="el" href="struct_x_csu_dma___configure.html#af2b9f211561ad313b726a60104afc32e">XCsuDma_Configure::TimeoutValue</a>, <a class="el" href="group__csudma__v1__0.html#ga668128c78f38748fb04d519246453033">XCSUDMA_CTRL2_ACACHE_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gab682491284b66d39496860a8333951c7">XCSUDMA_CTRL2_ACACHE_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga56c33f23233637055b848282bbb29cb6">XCSUDMA_CTRL2_MAXCMDS_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gabba0bc92253474154042e7eec30f531a">XCSUDMA_CTRL2_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#gac388240ecd8b78fe7a9051eb065e1d00">XCSUDMA_CTRL2_ROUTE_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gaba47338630b6e8aaa756aa442e886bc0">XCSUDMA_CTRL2_ROUTE_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#gad9d80f9c720cd3539b8086c467038432">XCSUDMA_CTRL2_TIMEOUT_EN_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gad4d0b2a2d8b593ac49f879567fd2f076">XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga9bc4b8e583b6c947023490e817352340">XCSUDMA_CTRL2_TIMEOUT_PRE_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gad1b3913111c69b6bd2be606dbe341ab4">XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga0e6766f31a6332796f3b8ff912c786e5">XCSUDMA_CTRL_APB_ERR_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gae7479f63823b9eb5f36139fd7414e56a">XCSUDMA_CTRL_APB_ERR_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#gae3c25e9c83a1e84d061746fa01142305">XCSUDMA_CTRL_BURST_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gaf44a7c00dd4ffbd3405b66a8fac60860">XCSUDMA_CTRL_BURST_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#gad5e388818030cd2ca04d9dc867440329">XCSUDMA_CTRL_ENDIAN_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga19e7f9c690bdf3c1633ea60845ca1285">XCSUDMA_CTRL_ENDIAN_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga083616ad7e4d22a9abfd3ab959c1eae4">XCSUDMA_CTRL_FIFO_THRESH_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga0ebe79007915c3f88a41b75168fbe8ff">XCSUDMA_CTRL_FIFO_THRESH_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga1d0f942367f084568b2adfb2b074443a">XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gaba325b1173d26c916097badcff6ab3d5">XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga8f46672097f2d6533df165bbc7bdf0e6">XCSUDMA_CTRL_TIMEOUT_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga0084f3cdeacc4098f70521b50006025d">XCSUDMA_CTRL_TIMEOUT_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">u32 XCsuDma_GetIntrMask </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>

<p>This function returns the interrupt mask to know which interrupts are enabled and which of them were disaled. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The current interrupt mask. The mask indicates which interrupts are enabled/disabled. 0 bit represents .....corresponding interrupt is enabled. 1 bit represents .....Corresponding interrupt is disabled. To interpret returned mask use XCSUDMA_IXR_SRC_MASK........For source channel XCSUDMA_IXR_DST_MASK........For destination channel</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#ga6072e9b915ebf29b27cddaa7478aade0">XCSUDMA_I_MASK_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">u32 XCsuDma_GetSize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function returns the size of the data yet to be transfered from memory to CSU_DMA or CSU_DMA to memory based on the channel selection. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Size is amount of data yet to be transfered.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, <a class="el" href="group__csudma__v1__0.html#gaf5d3e01cba7a5d0029901f690007a9c0">XCSUDMA_SIZE_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#gae1d5689d4fbd05c2e7f6b2a34bcbfb09">XCSUDMA_SIZE_SHIFT</a>, and <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">void XCsuDma_IntrClear </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
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          <td>)</td>
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<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>

<p>This function clears interrupt(s). </p>
<p>Every bit set in Interrupt Status Register indicates that a specific type of interrupt is occurring, and this function clears one or more interrupts by writing a bit mask to Interrupt Clear Register.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Mask</td><td>is the mask to clear. Bit positions of 1 will be cleared. Bit positions of 0 will not change the previous interrupt status. This mask is formed by OR'ing XCSUDMA_IXR_* bits defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#gab56adb100901bb2b042a842619064ce5">XCSUDMA_I_STS_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#gadfb7ef2922c9ceb4804bc87620c35134">XCSUDMA_IXR_DST_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga441edc2ec9eadb8093ac0ab41e0162d2">XCSUDMA_IXR_SRC_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">u32 XCsuDma_IntrGetStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>

<p>This function returns interrupt status read from Interrupt Status Register. </p>
<p>Use the XCSUDMA_IXR_*_MASK constants defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a> to interpret the returned value.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The pending interrupts of the CSU_DMA. Use th following masks to interpret the returned value. XCSUDMA_IXR_SRC_MASK - For Source channel XCSUDMA_IXR_DST_MASK - For Destination channel</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#gab56adb100901bb2b042a842619064ce5">XCSUDMA_I_STS_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">s32 XCsuDma_IsPaused </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#gad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a>&#160;</td>
          <td class="paramname"><em>Type</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This functions checks whether Channel's memory or stream is paused or not based on the given pause type. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Type</td><td>is type of the pause which needs to be checked.<ul>
<li>XCSUDMA_PAUSE_MEMORY(0) - Pause memory<ul>
<li>SRC Stops issuing of new read commands to memory.</li>
<li>DST Stops issuing of new write commands to memory.</li>
</ul>
</li>
<li>XCSUDMA_PAUSE_STREAM(1) - Pause stream<ul>
<li>SRC Stops transfer of data from FIFO to Stream.</li>
<li>DST Stops transfer of data from stream to FIFO.</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the pause status.<ul>
<li>TRUE if it is in paused state.</li>
<li>FALSE if it is not in pause state.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga8bbf92fafd6d0808e8db4a6b772e5b6f">XCSUDMA_CTRL_PAUSE_MEM_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gacdb2f8a8d2b8f782ffec216f6870c0a8">XCSUDMA_CTRL_PAUSE_STRM_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#ggad5ce08d197288cbdfb06941f1d46df87a4848b0d503f02b0b03be6cd1a14ef6a8">XCSUDMA_PAUSE_MEMORY</a>, <a class="el" href="group__csudma__v1__0.html#ggad5ce08d197288cbdfb06941f1d46df87a67086fbe749ed37f5928c211ee6aa5b8">XCSUDMA_PAUSE_STREAM</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_csu_dma___config.html">XCsuDma_Config</a> * XCsuDma_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>

<p>XCsuDma_LookupConfig returns a reference to an <a class="el" href="struct_x_csu_dma___config.html" title="This typedef contains configuration information for a CSU_DMA core. ">XCsuDma_Config</a> structure based on the unique device id, <em>DeviceId</em>. </p>
<p>The return value will refer to an entry in the device configuration table defined in the xcsudma_g.c file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique device ID of the device for the lookup operation.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>CfgPtr is a reference to a config record in the configuration table (in xcsudma_g.c) corresponding to <em>DeviceId</em>, or NULL if no match is found.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">void XCsuDma_Pause </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#gad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a>&#160;</td>
          <td class="paramname"><em>Type</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function pause the Channel data tranfer to/from memory or to/from stream based on pause type. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Type</td><td>is type of the pause to be enabled.<ul>
<li>XCSUDMA_PAUSE_MEMORY(0) - Pause memory<ul>
<li>SRC Stops issuing of new read commands to memory.</li>
<li>DST Stops issuing of new write commands to memory.</li>
</ul>
</li>
<li>XCSUDMA_PAUSE_STREAM(1) - Pause stream<ul>
<li>SRC Stops transfer of data from FIFO to Stream.</li>
<li>DST Stops transfer of data from stream to FIFO.</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="group__csudma__v1__0.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga8bbf92fafd6d0808e8db4a6b772e5b6f">XCSUDMA_CTRL_PAUSE_MEM_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gacdb2f8a8d2b8f782ffec216f6870c0a8">XCSUDMA_CTRL_PAUSE_STRM_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#ggad5ce08d197288cbdfb06941f1d46df87a4848b0d503f02b0b03be6cd1a14ef6a8">XCSUDMA_PAUSE_MEMORY</a>, <a class="el" href="group__csudma__v1__0.html#ggad5ce08d197288cbdfb06941f1d46df87a67086fbe749ed37f5928c211ee6aa5b8">XCSUDMA_PAUSE_STREAM</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">void XCsuDma_Resume </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#gad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a>&#160;</td>
          <td class="paramname"><em>Type</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function resumes the channel if it is in paused state and continues where it has left or no effect if it is not in paused state, based on the type of pause. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Type</td><td>is type of the pause to be Resume if it is in pause state.<ul>
<li>XCSUDMA_PAUSE_MEMORY(0) - Pause memory<ul>
<li>SRC Stops issuing of new read commands to memory.</li>
<li>DST Stops issuing of new write commands to memory.</li>
</ul>
</li>
<li>XCSUDMA_PAUSE_STREAM(1) - Pause stream<ul>
<li>SRC Stops transfer of data from FIFO to Stream.</li>
<li>DST Stops transfer of data from stream to FIFO.</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="group__csudma__v1__0.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga8bbf92fafd6d0808e8db4a6b772e5b6f">XCSUDMA_CTRL_PAUSE_MEM_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gacdb2f8a8d2b8f782ffec216f6870c0a8">XCSUDMA_CTRL_PAUSE_STRM_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#ggad5ce08d197288cbdfb06941f1d46df87a4848b0d503f02b0b03be6cd1a14ef6a8">XCSUDMA_PAUSE_MEMORY</a>, <a class="el" href="group__csudma__v1__0.html#ggad5ce08d197288cbdfb06941f1d46df87a67086fbe749ed37f5928c211ee6aa5b8">XCSUDMA_PAUSE_STREAM</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">s32 XCsuDma_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p><code>#include &lt;<a class="el" href="xcsudma_8h.html">xcsudma.h</a>&gt;</code></p>

<p>This function runs a self-test on the driver and hardware device. </p>
<p>Performs reset of both source and destination channels and checks if reset is working properly or not.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the self-test passed.<ul>
<li>XST_FAILURE otherwise.</li>
</ul>
</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csudma__v1__0.html#gad5e388818030cd2ca04d9dc867440329">XCSUDMA_CTRL_ENDIAN_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">void XCsuDma_SetConfig </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma___configure.html">XCsuDma_Configure</a> *&#160;</td>
          <td class="paramname"><em>ConfigurValues</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function cofigures all the values of CSU_DMA's Channels with the values of updated <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which needs to be set before the start of the data...">XCsuDma_Configure</a> structure. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">ConfigurValues</td><td>is a pointer to the structure <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which needs to be set before the start of the data...">XCsuDma_Configure</a> whose values are used to configure CSU_DMA core.<ul>
<li>SssFifoThesh When the DST FIFO level &gt;= this value, the SSS interface signal, "data_out_fifo_level_hit" will be asserted. This mechanism can be used by the SSS to flow control data that is being looped back from the SRC DMA.<ul>
<li>Range is (0x10 to 0x7A) threshold is 17 to 123 entries.</li>
<li>It is valid only for DST CSU_DMA IP.</li>
</ul>
</li>
<li>ApbErr When accessed to invalid APB the resulting pslerr will be<ul>
<li>0 - 1'b0</li>
<li>1 - 1'b1</li>
</ul>
</li>
<li>EndianType Type of endianness<ul>
<li>0 doesn't change order</li>
<li>1 will flip the order.</li>
</ul>
</li>
<li>AxiBurstType....Type of the burst<ul>
<li>0 will issue INCR type burst</li>
<li>1 will issue FIXED type burst</li>
</ul>
</li>
<li>TimeoutValue Time out value for timers<ul>
<li>0x000 to 0xFFE are valid inputs</li>
<li>0xFFF clears both timers</li>
</ul>
</li>
<li>FifoThresh......Programmed watermark value<ul>
<li>Range is 0x00 to 0x80 (0 to 128 entries).</li>
</ul>
</li>
<li>Acache Sets the AXI CACHE bits on the AXI Write/Read channel.<ul>
<li>Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] for DST channel are always 1, we need to configure remaining 3 signal support (Bufferable, Read allocate and Write allocate). Valid inputs are:</li>
<li>0x000 - Cacheable, but do not allocate</li>
<li>0x001 - Cacheable and bufferable, but do not allocate</li>
<li>0x010 - Cacheable write-through, allocate on reads only</li>
<li>0x011 - Cacheable write-back, allocate on reads only</li>
<li>0x100 - Cacheable write-through, allocate on writes only</li>
<li>0x101 - Cacheable write-back, allocate on writes only</li>
<li>0x110 - Cacheable write-through, allocate on both reads and writes</li>
<li>0x111 - Cacheable write-back, allocate on both reads and writes</li>
</ul>
</li>
<li>RouteBit To select route<ul>
<li>0 : Command will be routed normally</li>
<li>1 : Command will be routed to APU's cache controller</li>
</ul>
</li>
<li>TimeoutEn To enable or disable time out counters<ul>
<li>0 : The 2 Timeout counters are disabled</li>
<li>1 : The 2 Timeout counters are enabled</li>
</ul>
</li>
<li>TimeoutPre Set the prescaler value for the timeout in clk (~2.5ns) cycles<ul>
<li>Range is 0x000(Prescaler enables timer every cycles) to 0xFFF(Prescaler enables timer every 4096 cycles)</li>
</ul>
</li>
<li>MaxOutCmds Controls the maximumum number of outstanding AXI read commands issued.<ul>
<li>Range is 0x0(Up to 1 Outstanding Read command allowed) to 0x8 (Up to 9 Outstanding Read command allowed)</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>To use timers timeout value Timeout enable field should be enabled. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___configure.html#a984f69d8fa925618e85800ba8fd2d155">XCsuDma_Configure::Acache</a>, <a class="el" href="struct_x_csu_dma___configure.html#a7ca88dbe204c7b24ce7e529da53e1ae2">XCsuDma_Configure::ApbErr</a>, <a class="el" href="struct_x_csu_dma___configure.html#a1aeadd99f4f96da636b9cb0c2be21c09">XCsuDma_Configure::AxiBurstType</a>, <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma___configure.html#a4d1217d471a558f54534c15213bbb264">XCsuDma_Configure::EndianType</a>, <a class="el" href="struct_x_csu_dma___configure.html#af17af84045f926ff8e386509cc0c9aee">XCsuDma_Configure::FifoThresh</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="struct_x_csu_dma___configure.html#acdf6a30da74f891648e17d1ce9bfadae">XCsuDma_Configure::MaxOutCmds</a>, <a class="el" href="struct_x_csu_dma___configure.html#ac6f8c811d5b1ecf86d37091fc132717e">XCsuDma_Configure::RouteBit</a>, <a class="el" href="struct_x_csu_dma___configure.html#a524260e03c75bc8745da0e4b7dca71ed">XCsuDma_Configure::SssFifoThesh</a>, <a class="el" href="struct_x_csu_dma___configure.html#a2f45ba702e0487ed32152186339d7052">XCsuDma_Configure::TimeoutEn</a>, <a class="el" href="struct_x_csu_dma___configure.html#a00365f4d0973fcb3fd39382312775748">XCsuDma_Configure::TimeoutPre</a>, <a class="el" href="struct_x_csu_dma___configure.html#af2b9f211561ad313b726a60104afc32e">XCsuDma_Configure::TimeoutValue</a>, <a class="el" href="group__csudma__v1__0.html#ga668128c78f38748fb04d519246453033">XCSUDMA_CTRL2_ACACHE_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gab682491284b66d39496860a8333951c7">XCSUDMA_CTRL2_ACACHE_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga56c33f23233637055b848282bbb29cb6">XCSUDMA_CTRL2_MAXCMDS_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gabba0bc92253474154042e7eec30f531a">XCSUDMA_CTRL2_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga2994ec3a4ddd8feadffbdeafa27fdd8a">XCSUDMA_CTRL2_RESERVED_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gac388240ecd8b78fe7a9051eb065e1d00">XCSUDMA_CTRL2_ROUTE_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gaba47338630b6e8aaa756aa442e886bc0">XCSUDMA_CTRL2_ROUTE_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#gad9d80f9c720cd3539b8086c467038432">XCSUDMA_CTRL2_TIMEOUT_EN_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gad4d0b2a2d8b593ac49f879567fd2f076">XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga9bc4b8e583b6c947023490e817352340">XCSUDMA_CTRL2_TIMEOUT_PRE_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gad1b3913111c69b6bd2be606dbe341ab4">XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga0e6766f31a6332796f3b8ff912c786e5">XCSUDMA_CTRL_APB_ERR_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gae7479f63823b9eb5f36139fd7414e56a">XCSUDMA_CTRL_APB_ERR_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#gae3c25e9c83a1e84d061746fa01142305">XCSUDMA_CTRL_BURST_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gaf44a7c00dd4ffbd3405b66a8fac60860">XCSUDMA_CTRL_BURST_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#gad5e388818030cd2ca04d9dc867440329">XCSUDMA_CTRL_ENDIAN_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga19e7f9c690bdf3c1633ea60845ca1285">XCSUDMA_CTRL_ENDIAN_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga083616ad7e4d22a9abfd3ab959c1eae4">XCSUDMA_CTRL_FIFO_THRESH_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga0ebe79007915c3f88a41b75168fbe8ff">XCSUDMA_CTRL_FIFO_THRESH_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga1d0f942367f084568b2adfb2b074443a">XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK</a>, <a class="el" href="group__csudma__v1__0.html#gaba325b1173d26c916097badcff6ab3d5">XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga8f46672097f2d6533df165bbc7bdf0e6">XCSUDMA_CTRL_TIMEOUT_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga0084f3cdeacc4098f70521b50006025d">XCSUDMA_CTRL_TIMEOUT_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#gaf15d6d8d487734165214850984ac00f2">XCsuDma_IsBusy</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">void XCsuDma_Transfer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csudma__v1__0.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>Addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>EnDataLast</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xcsudma_8c.html">xcsudma.c</a>&gt;</code></p>

<p>This function sets the starting address and amount(size) of the data to be transfered from/to the memory through the AXI interface. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>represents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Addr</td><td>is a 64 bit variable which holds the starting address of data which needs to write into the memory(DST) (or read from the memory(SRC)). </td></tr>
    <tr><td class="paramname">Size</td><td>is a 32 bit variable which represents the number of 4 byte words needs to be transfered from starting address. </td></tr>
    <tr><td class="paramname">EnDataLast</td><td>is to trigger an end of message. It will enable or disable data_inp_last signal to stream interface when current command is completed. It is applicable only to source channel and neglected for destination channel.<ul>
<li>1 - Asserts data_inp_last signal.</li>
<li>0 - data_inp_last will not be asserted.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Data_inp_last signal is asserted simultaneously with the data_inp_valid signal associated with the final 32-bit word transfer. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a5ae2bdbc7b887da084a72d1447332a90">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="group__csudma__v1__0.html#ga167f814ecf53fd2228490b5b6d5431df">XCSUDMA_ADDR_LSB_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga23841a10691cb51210298b0614e67573">XCSUDMA_ADDR_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga4d6c9218a21c89c884ef15a38956469b">XCSUDMA_ADDR_MSB_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#ga76fcd0f2a0c7ebc2058f231a944c7109">XCSUDMA_ADDR_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csudma__v1__0.html#gaf0a5114bb4e675c0e9d933a2d235ac6f">XCSUDMA_LAST_WORD_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga29841329ffd65ef1b49870b89171188d">XCSUDMA_MSB_ADDR_MASK</a>, <a class="el" href="group__csudma__v1__0.html#ga8cb51c5b9c07f84acf19defd57ae764b">XCSUDMA_MSB_ADDR_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>, <a class="el" href="group__csudma__v1__0.html#gab57550413ed1c53f70a33ad4b90965eb">XCSUDMA_SIZE_MAX</a>, <a class="el" href="group__csudma__v1__0.html#gaf5d3e01cba7a5d0029901f690007a9c0">XCSUDMA_SIZE_OFFSET</a>, <a class="el" href="group__csudma__v1__0.html#gae1d5689d4fbd05c2e7f6b2a34bcbfb09">XCSUDMA_SIZE_SHIFT</a>, <a class="el" href="group__csudma__v1__0.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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